1. Field of the Invention
The present invention relates to a locking-status judging circuit for a digital PLL (Phase Locked Loop) circuit, which judges whether or not the digital PLL circuit locks on an input signal.
2. Description of the Related Art
Recently, an optical disc, which is recorded with an information signal such as a video signal and an audio signal, has been introduced into markets, wherein the information signal is converted into a digital signal, compressed, encoded and modulated digitally. When reproducing such an optical disc, the digitally modulated signal that is recorded in the optical disc is read out, and a clock signal for decoding the digitally modulated signal is extracted. By using the extracted clock signal, the digitally modulated signal is demodulated, and then the compression encoded information signal is decoded. In other words, a clock signal is generated by inputting a signal that is reproduced from an optical disc into a digital PLL (Phase Locked Loop) circuit. Then, by using the clock signal, an information signal that is recorded in the optical disc is reproduced.
In this connection, if a lock-state detector circuit enables to detect immediately a status of the digital PLL circuit whether the digital PLL circuit is in synchronism with an input signal, that is, in a lock-state or out of synchronization, that is, in an unlock-state, the digital PLL circuit enables to be advanced to the lock-state by increasing a loop gain of the digital PLL circuit in case of the unlock-state. On the contrary, in case of the lock-state, by reducing the loop gain of the digital PLL circuit, the digital PLL circuit enables to be hardly affected by a noise signal component to be possibly inputted and enables to obtain a clock signal of which frequency is stable. Consequently, an optical disc reproducing apparatus, which enables to start to reproduce an information signal recorded in an optical disc immediately, enables to be realized.
Further, the optical disc reproducing apparatus enables to reproduce a signal to be demodulated in higher stability although the signal contains excessive phase fluctuation components.
With referring to a drawing, operations of a PLL circuit are depicted.
FIG. 10 is a block diagram of a conventional PLL circuit provided with a lock-state detecting section according to the prior art.
As shown in FIG. 10, a conventional PLL circuit having a lock-state detector function is composed of a PLL section 8 and a lock-state detecting section 9. The PLL section 8 is further composed of a phase comparator circuit 81, a loop filter 82, and a voltage controlled oscillator 83. The lock-state detecting section 9 is further composed of a phase difference detector circuit 91 and a lock-state detector circuit 92.
An input signal having a noise component and a phase fluctuation component is supplied to one input terminal of the phase comparator circuit 81 and the phase difference detector circuit 91 respectively. The other input terminal of the phase comparator circuit 81 and the phase difference detector circuit 91 is respectively supplied with an oscillator output signal that is generated by the voltage controlled oscillator 83.
The phase comparator circuit 81 detects a phase difference between the input signal and the oscillator output signal outputted from the voltage controlled oscillator 83, and results in outputting an error signal based on the phase difference. The error signal is inputted into the loop filter 82, and a low frequency component of the error signal is boosted through an accumulation process therein. The error signal of which low frequency component is boosted by the loop filter 82 is inputted into the voltage controlled oscillator 83.
The voltage controlled oscillator 83 oscillates at a frequency in response to the inputted error signal and outputs an oscillator output signal. Then, a clock signal for driving other digital circuit (not shown) such as a demodulator circuit for a digitally modulated signal and a decoder circuit for a compression encoded signal is generated by using the oscillator output signal.
The phase difference detector circuit 91 detects a phase difference between the inputted two signals, the input signal and the oscillator output signal through the synchronous detection. In other words, the phase difference detector circuit 91 outputs a phase error signal in low level in case the conventional PLL circuit locks on the input signal. On the contrary, in case the conventional PLL circuit does not lock on the input signal or the input signal contains excessive noise components and excessive phase fluctuation components, the phase difference detector circuit 91 outputs a phase error signal in high level.
The lock-state detector circuit 92 compares an absolute value of the phase error signal with a prescribed reference value, and detects a status of the conventional PLL circuit. The status of the conventional PLL circuit is detected as the unlock-state in case the absolute value of the phase error signal is larger than the prescribed reference value.
An optical disc reproducing apparatus installed with the PLL section 8 and the lock-state detecting section 9 conducts to demodulate a reproduced digitally modulated signal and decodes a compression encoded information signal on the basis of the detected signal in the lock-state.
The Japanese publication of unexamined patent applications No. 2002-358739 discloses that detecting the unlock-state of the PLL circuit is realized by detecting a phase error signal such that an average of phase error signals in the prescribed time period exceeds the predetermined value, wherein the phase error signal is the output signal from the phase comparator of the PLL circuit. Unstableness of phase synchronism in the PLL circuit enables to be detected by detecting the unlock-state of the PLL circuit. By detecting a status of phase synchronism in the PLL circuit, the circuit operation in the error correction section is stopped when unstableness is detected. Consequently, the optical disc reproducing apparatus in which power consumption of the circuit is reduced is realized.
Further, the Japanese Patent No. 3028955 discloses the method of detecting a lock-state in the PLL locking circuit. According to the Japanese Patent No. 3028955, by comparing a phase error signal with the prescribed reference value, the PLL locking circuit outputs a phase error signal, which is utilized for judging whether the PLL circuit is in the lock-state or not, only when a phase error signal falls below the prescribed reference value continuously a plurality of times that exceeds the prescribed number of times.
However, according to the method of reproducing data disclosed in the Japanese publication of unexamined patent applications No. 2002-358739, it is hardly discriminated whether a phase error signal in higher level to be detected is generated on the basis of a signal having a short inversion interval or the phase error signal is generated by the PLL circuit that is in the unlock-state, in case a signal having large phase fluctuation such as a signal having a short inversion interval is inputted into the reproducing apparatus although the PLL circuit is in the lock-state when reproducing an optical disc. Particularly, it is hard to discriminate the distinction when a higher frequency range of the signal to be inputted is attenuated due to deterioration of transfer characteristics that occurs in a process from recording to reproducing.
Further, in case loop gain of the PLL circuit is increased to compensate the attenuated high frequency component so as to shift the PLL circuit from the unlock-state to the lock-state, it is difficult to discriminate whether a phase error signal that is detected by the phase difference detector circuit 91 is generated on the basis of phase fluctuation of the signal to be inputted or the phase error signal is generated by the PLL circuit that is in the unlock-state.
Furthermore, with respect to the method of detecting the lock and unlock states disclosed in the Japanese Patent No. 3028955, further details are given to a specific case in which an input signal to be detected whether it is in the lock-state or the unlock-state is obtained by reproducing a n optical disc.
When reproducing an optical disc, an input signal having a long inversion interval is hardly affected by deterioration of transfer characteristics, so that a PLL circuit easily locks on the input signal, and discriminating the lock-state is also easy. However, in case of an input signal having a short inversion interval, the input signal is easily affected by deterioration of transfer characteristics in a higher frequency range, and resulting in detecting phase error larger due to enhancing high frequency range so as to compensate the deterioration of the high frequency range. Consequently, phase error exceeding a reference value is often detected. On the other hand, in case of a signal having a short inversion interval, such a signal is often contained in the input signal at random. Therefore, when a signal having a short inversion interval is inputted into the PLL circuit in succession, the locking status of the PLL circuit might be detected as the unlock-state although the PLL circuit locks on the input signal. In other words, the method of judging the locking status of the PLL circuit disclosed in the Japanese Patent No. 3028955 sometimes misjudges.